Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association
نویسندگان
چکیده
This paper suggests the systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massive parallelism and can be extended by cascading identical chips.
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